Arm TechCon 2017 Schedule

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A Standardized, Predictable On-chip Power Control Infrastructure

Location: Ballroom F
Pass Type: All-Access Pass - Get your pass now!
Track: High-Efficiency Systems
Format: 50-Minute Technical Session
Audience Level: Intermediate
Recording: TBD

Clock and power management on modern SoCs with many domains and power states requires careful consideration of sequencing, asynchronous signalling and communication between functional blocks and power management. Implementing this complex infrastructure is often a time consuming and error prone. Mistakes can lead to end devices that use too much power, or do not function at all.
This talk highlights proposes a solution including a standardised AMBA interface to communicate clock and power intent, an introduction to the Arm Power Control System Architecture, and an overview of the critical blocks that implement this standard.
Result: low-power SoC without the hassle