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Back-end timing closure for SoC interconnects is an obstacle for engineers who are migrating to smaller semiconductor geometries and FinFET transistors in Arm-based SoC Designs. The issue adds significant delay to project schedules. But design engineers can reduce delays and close timing sooner by assigning higher priority to the interconnect earlier in the SoC planning stages so that the connections between IP blocks are optimized for functionality, location, performance, latency, power and area. This session will detail an innovative interconnect topology optimization processes implemented during the front-end of design to slash more than 30 schedule days.
Get to market sooner with Arm-based SoCs in advanced geometries by optimizing interconnect communication paths during front-end design. By performing front-end Network-on-Chip timing automation and analysis, physical synthesis results become much more predictable, thereby reducing iterations in the backend and greatly accelerating the entire physical design process.