Arm TechCon 2017 Schedule

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Addressing 7nm DSU Design Challenges Using the Cadence Digital Implementation Flow

Location:  Ballroom G
Pass Type: All-Access Pass - Get your pass now!
Track: Silicon Design
Format: 50-Minute Technical Session
Audience Level: All
Recording: TBD

Arm DSU (DynamIQ Shared Unit) provides the connectivity between different Arm CPUs enabling communication with other system components. Implementing DSU logic presents a number of physical challenges due to tightly coupled module placement which is critical for timing closure, many floor plan macro channels leading to congestion and long signal integrity (SI) sensitive routes. These concerns become even more significant at the 7nm process node. Arm will share experience gained implementing a complete 7nm DSU configuration. Topics such as 7nm implementation, efficient long wire optimization, SI avoidance and repair, and signoff-accurate timing closure will be covered.

Takeaway

Learn about Arm DynamIQ technology and how to use Cadence Digital Implementation flow to implement 7nm Arm DSU Cluster.