Arm TechCon 2017 Schedule

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Applying Asymmetric Heterogeneous Architecture using Arm Cortex-A & Cortex-M Processors

Pass Types: All-Access Pass, Training Pass, Arm Mbed Connect Pass, Expo Pass - Get your pass now!
Track: Arm Theater (Free)
Format: 30-Minute Arm Theater (Free)
Audience Level: Intermediate
Recording: TBD

This session shows how we built a balancing robot using an asymmetric heterogeneous Arm SoC sporting Cortex-A7 and Cortex-M4 cores. The NXP i.MX7 family integrates this architecture with a shared bus topology. We will discuss the hardware & software components available to simplify core isolation and communication among the independent operating systems: Linux on the Cortex-A7 core and FreeRTOS on the Cortex-M4 core.

Takeaway

What is a asymmetric heterogeneous multiprocessing architecture - in particular, its implementation using Cortex-A & Cortex-M - and how it is being used in a real-world application. What software challenges exist and what frameworks are available today.

Intended Audience

Embedded hardware & software engineers and system designers balancing the need for real-time control with the conflicting need for graphical UI, high speed interfaces and/or heavy multiprocessing all while minimizing design size, cost & complexity. Some knowledge of embedded Linux and/or FreeRTOS is recommended.