Arm TechCon 2017 Schedule

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Early RTL Power Analysis on Next-Gen Arm GPUs Using Cadence Digital Implementation Tools

Location:  Ballroom G
Pass Type: All-Access Pass - Get your pass now!
Track: Silicon Design
Format: 50-Minute Technical Session
Audience Level: All
Recording: TBD

The most efficient place to reduce total power is during initial architectural design, which requires high-speed and capacity RTL power analysis. Arm will describe RTL- and netlist-based power analysis flows which have been developed to enable power reduction in CPU and GPU cores. Topics such as average and time-based analysis, generating stimulus from software and hardware simulators, directly integrating these vectors into the power analysis flows, mapping RTL vectors to netlists to avoid lengthy netlist simulation runs, and using power analysis results to reduce total power during final implementation will all be covered.

Takeaway

Learn how to use Cadence Digital Implementation tools to quickly analyze and reduce power for the latest Arm CPU and GPU cores.