Arm TechCon 2017 Schedule

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Functional Safety for Arm Application Processors in R-Car Third Gen With Supporting ASIL B

  • Tung Nguyen | Senior engineer, Renesas Design Vietnam Ltd.
Location: Ballroom H
Pass Type: All-Access Pass - Get your pass now!
Track: Automotive, Industrial & Functional Safety
Format: 50-Minute Technical Session
Audience Level: All
Recording: TBD

It becomes common requirement to comply with ISO26262 for functional safety in automotive systems. This work presents a safety mechanism achieving ISO26262 ASIL B on quad-core Arm Cortex-A57 processor and quad-core Arm Cortex-A53 processor in R-Car third generation SoC. The mechanism consists of hardware built-in self-test (BIST) for fault detection, and time slicing technique for test time optimization. The trade-off between fault detect coverage and test time is a key focus of runtime test design. By controlling number of test patterns and testing time, 90% of fault detection coverage was measured in 1.28ms of test time without degradation of overall application performance including audio application running on Arm Cortex-A53 core.

Takeaway

The audience will gain a benefit of:
+ Hardware built-in self-test with time slicing technique is an advantaged solution for functional safety.
+ The trade-off between fault detect coverage and test time is a key focus.
+ Separating mission between cores as well as guarantee of CPU state from multi-cache stores is a key requirement.