ARM TechCon 2015 Schedule

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  • Introspective Performance Modeling and Analysis with All Programmable SoCs

    Graham Schelle  |  Senior Research Staff, Xilinx
    Location:  Ballroom H
    Format: 50-minute Technical Session
    Track: Tools & Implementation
    Pass Type: Conference Pass - Get your pass now!
    Vault Recording: TBD
    Audience Level: All

    Current system on chips are often tightly coupled to FPGA programmable logic. These truly general purpose SoCs are highly configurable and not optimized to a single application domain. System architects can therefore move kernels from software to hardware-accelerators and define custom datapaths optimizing application performance.

    This highly configurable performance can be seen as highly complex. We address the complexity challenge by introducing an entirely new System Performance Analysis and Modeling methodology allowing SoC designers to explore performance across register settings, software benchmarks and hardware traffic patterns targeting off-the-shelf development boards. All settings are software configurable on live silicon allowing quick-turn scenario exploration to de-risk and validate SoC performance expectations.


    New tools and methodology for achieving system-level performance goals in All Programmable HW and SW SoCs are introduced. We report new approaches to analyzing and optimizing system-level performance of these complex SoCs targeting performance 'hotspots' caused by contention for critical shared resources such as interconnect and external memories.

    Intended Audience

    Audience should be familiar with embedded systems, ARM SoC architectures and AXI.