Arm TechCon 2017 Schedule

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Meeting the Coherent Design Challenge: Developing & Debugging AMBA-5 CHI Implementations

Location: Ballroom H
Pass Type: All-Access Pass - Get your pass now!
Track: Silicon Design
Format: 50-Minute Technical Session
Audience Level: Intermediate
Recording: TBD

Today's SoCs commonly include multiple processors, leading to challenges with cache coherency. We explain how Arm's advanced AMBA 5 CHI protocol can help to meet these challenges, and outline in detail on-chip monitoring and analytic techniques that need to be utilized to allow to the debug and performance-optimization of coherent designs. By non-intrusive, wire-speed monitoring of processes like bus snooping, at the transaction level of the fabric, engineers get rich insight into the operation of the system during real use, improving QoS in coherency management across the device, identifying problems and improving overall performance.

Takeaway

You will learn:

  • Why coherent design is required
  • The benefits of using the AMBA 5 CHI standard
  • Some practical challenges of CHI implementation with real-world examples
  • How non-intrusive on-chip analytics can be used for CHI debug and optimization
  • How transaction-level monitors can provide rich system information to help engineers develop and improve their coherent designs